logo EDITE Sylvain FERUGLIO
Identité
Sylvain FERUGLIO
État académique
Thèse soutenue le 2005-12-12
Titulaire d'une HDR (ou équivalent)
Laboratoire: personnel permanent
Direction de thèses (depuis 2007)
1
Voisinage
Ellipse bleue: doctorant, ellipse jaune: docteur, rectangle vert: permanent, rectangle jaune: HDR. Trait vert: encadrant de thèse, trait bleu: directeur de thèse, pointillé: jury d'évaluation à mi-parcours ou jury de thèse.
Productions scientifiques
edite:133279232247
A Design Approah for Networks of self-Sampled All-Digital Phase-Locked Loops
20th European Conference on Circuit theory and Design (ECCTD'11),, Linköping, Sweden 2011
edite:133279232864
A Self-Sufficient Digitally Controlled Ring Oscillator Compensated for Supply Voltage Variation
The IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Liban 2011
edite:133279233282
An Analytical Model Of The Oscillation Period For Tri-State Inverter Based DCO
The IEEE International Conference on Microelectronics (ICM), Hammamet, Tunisie 2011
edite:1332792366214
FPGA Implementation of Reconfigurable ADPLL Network for Distributed Clock Generation
accepted in 2011 International Conference on Field Programmable Technology 2011
edite:1332792531995
Bruit dans les oscillateurs contrôlés, application à un réseau de PLLs couplée
Colloque du GDR SOC-SIP 2009
edite:13327925521157
Low-Temperature Electrical Characterization of Fully Depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 Gate Stack for the 32-nm Technology Node
Vol. 49, No. 11, pp. 605-610 2009