Manycore processors are a way to face the always growing demand in digital data processing. However, by putting closer distinct and possibly private data, they open up new security breaches. Splitting the architecture into several partitions managed by a hypervisor is a way to enforce isolation between the running virtual machines. Thanks to their high number of cores, these architectures can mitigate the impact of dedicating cores both to the virtual machines and the hypervisor, while allowing an efficient execution of the virtualized operating systems. We present such an architecture allowing the execution of fully virtualized multicore operating systems benefiting of hardware cache coherence. The physical isolation is made by the means of address space via the introduction of a light hardware module similar to a memory-management unit at the network-on-chip entrance, but without the drawback of relying on a page table. We designed a cycle-accurate virtual prototype of the architecture , controlled by a light blind hypervisor with minimum rights, only able to start and stop virtual machines. Experiments made on our virtual prototype shows that our solution has a low time overhead – typically 3% on average.
ISSN: 0141-9331 EISSN: 0141-9331 Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) http://hal.upmc.fr/hal-01382444 Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, <10.1016/j.micpro.2016.09.008>ARRAY(0x7f5470672cb0) 2016