logo EDITE Eric LAO
Identité
Eric LAO
État académique
Thèse en cours...
Sujet: Environnement Intégré pour la conception de circuits mixtes CMOS
Direction de thèse:
Laboratoire:
Voisinage
Ellipse bleue: doctorant, ellipse jaune: docteur, rectangle vert: permanent, rectangle jaune: HDR. Trait vert: encadrant de thèse, trait bleu: directeur de thèse, pointillé: jury d'évaluation à mi-parcours ou jury de thèse.
Productions scientifiques
oai:hal.archives-ouvertes.fr:hal-01484414
Semi-automated analog placement
International audience
Analog design remains a manual task because of the complexity of the interactions among devices. Automation tools dedicated to analog circuits are not as mature as the digital automation ones, but have been improved a lot at a point that they can help at individual steps in the analog design flow. Our approach is to propose a semi-automated analog placement controlled by the designer, following an organization in row similar to a digital circuit structure. The results show the ability of our tool at generating multiple layouts respecting designer's constraints.
Electronics, Circuits and Systems (ICECS), 2016 IEEE International Conference on 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) https://hal.archives-ouvertes.fr/hal-01484414 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2016, Monte Carlo, Monaco. Electronics, Circuits and Systems (ICECS), 2016 IEEE International Conference on, pp.432 - 433, 2016, <10.1109/ICECS.2016.7841227>ARRAY(0x7f04018886d8) 2016-12-11
oai:hal.archives-ouvertes.fr:hal-01473702
Semi-Automated Analog Placement based on Margin Tolerances
International audience
Digital circuit design is extensively assisted by modern automation tool unlike analog design which is still a manual task because of the complexity of the interactions between devices. This paper presents a semi-automated analog placement based on margin tolerances controlled by the designer by creating analog circuits organized in row similar to digital circuits structure. The results show the ability of our tool at generating multiple layouts respecting designer's constraints.
The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016) http://hal.upmc.fr/hal-01473702 The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), Oct 2016, Kyoto, Japan. <http://sasimi.jp/new/sasimi2016/> http://sasimi.jp/new/sasimi2016/ARRAY(0x7f03ffd02d38) 2016-10-24