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Identité
Tian BAN
État académique
Thèse soutenue le 2012-09-04
Sujet: Reliable Digital IPs under Deep-submicron Technologies
Direction de thèse:
Laboratoire:
Voisinage
Ellipse bleue: doctorant, ellipse jaune: docteur, rectangle vert: permanent, rectangle jaune: HDR. Trait vert: encadrant de thèse, trait bleu: directeur de thèse, pointillé: jury d'évaluation à mi-parcours ou jury de thèse.
Productions scientifiques
TB:NEWCAS2010
A Simple Fault-tolerant Digital Voter Circuit in TMR Nanoarchitectures
IEEE International NEWCAS Conference, Montreal, Canada 2010-06
oai:hal.archives-ouvertes.fr:hal-00637634
Progressive module redundancy for fault-tolerant designs in nanoelectronics
Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best subset among possible redundant architectures. It builds upon the progressive module redundancy technique and the block grading concept. Furthermore, this method is not constrained on TMR but extends to 5MR. Experiment results demonstrate its advantages in efficiency, reliability and cost. The proposed method points out a new direction of economical redundant fault-tolerant designs for nanoelectronics.
Proceedings of 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysisproceeding with peer review 2011-10-03
oai:hal.archives-ouvertes.fr:hal-00637639
A simple fault-tolerant digital voter circuit in TMR nanoarchitectures
Nanoelectronic systems are now more and more prone to faults and defects, permanent or transient. Redundancy techniques are implemented widely to increase the reliability, especially the TMR - Triple Modular Redundancy. However, many researchers assume that the voter is perfect and this may not be true. This paper proposes a simple but effective fault-tolerant voter circuit which is more reliable and less expensive. Experimental results demonstrate its improvement over the former TMR structures
NEWCAS Conference (NEWCAS), 2010 8th IEEE International 2010 8th IEEE International NEWCAS Conference (NEWCAS)proceeding with peer review 2010-06-20
oai:hal.archives-ouvertes.fr:hal-00637373
Reliability analysis based on significance
Due to the expected increase of defects and errors in circuits based on deep submicron technologies, reliability has become an important design criterion. As reliability improvement is generally achieved by adding redundancy, identify and classify critical blocks of a circuit is a major concern. This work presents two new classification methods regarding the significance of a block with respect to the reliability of a circuit. One gives the criticality of each block for the circuit reliability and the other indicates which priority should be given to each block in a process of adding redundancy. Thus, the proposed methods provide key information for the designer who is looking for efficient solutions of reliability monitoring or reliability improvement.
Argentine School of Micro-Nanoelectronics Technology and Applications (EAMTA) Argentine School of Micro-Nanoelectronics Technology and Applications (EAMTA)proceeding with peer review 2011-09-15
oai:hal.archives-ouvertes.fr:hal-00637626
Progressive module redundancy for fault-tolerant designs in nanoelectronics
Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best subset among possible redundant architectures. It builds upon the progressive module redundancy technique and the block grading concept. Furthermore, this method is not constrained on TMR but extends to 5MR. Experiment results demonstrate its advantages in efficiency, reliability and cost. The proposed method points out a new direction of economical redundant fault-tolerant designs for nanoelectronics.
Microelectronics Reliabilitypeer-reviewed article 2011-09-16
oai:hal.archives-ouvertes.fr:hal-00637642
Optimized Robust Digital Voter in TMR Designs
Proceedings of Colloque National GdR SoC-SiPproceeding, seminar, workshop without peer review 2011-06-15
oai:hal.archives-ouvertes.fr:hal-00728879
Majority voter: Signal probability, reliability and error bound characteristics
The importance of reliability in majority voter is due to its application in both conventional fault-tolerant design and novel nanoelectronic systems. A better understanding of signal probability, functional/signal reliability and error bound of majority voter is discussed in this paper. We analyze these parameters by boolean difference. The equations derived in this paper present the characteristics of error propagations in majority voter, and reveal the conditions that TMR (Triple Module Redundancy) technique requires. The results show the critical importance of error characteristics of majority voter, as used in fault-tolerant designs.
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium onpeer-reviewed article 2012-09-03
Soutenance
Thèse: Méthodes et architectures basées sur la redondance modulaire pour circuits combinatoires tolérants aux fautes
Soutenance: 2012-09-04