logo EDITE Arwa BEN DHIA
Identité
Arwa BEN DHIA
État académique
Thèse soutenue le 2014-11-14
Sujet: Defect Tolerance in FPGA
Direction de thèse:
Laboratoire:
Voisinage
Ellipse bleue: doctorant, ellipse jaune: docteur, rectangle vert: permanent, rectangle jaune: HDR. Trait vert: encadrant de thèse, trait bleu: directeur de thèse, pointillé: jury d'évaluation à mi-parcours ou jury de thèse.
Productions scientifiques
oai:hal.archives-ouvertes.fr:hal-01062063
A Defect-Tolerant Multiplexer Using Differential Logic for FPGAs
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IEEE 21st Mixed Design of Integrated Circuits and Systems Conference (MIXDES) IEEE 21st Mixed Design of Integrated Circuits and Systems Conference (MIXDES)conference proceeding 2014-06
oai:hal.archives-ouvertes.fr:hal-01062073
A Defect-tolerant Cluster in a Mesh SRAM-based FPGA
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International Conference on Field-Programmable Technology (ICFPT) International Conference on Field-Programmable Technology (ICFPT)conference proceeding 2013-12
oai:hal.archives-ouvertes.fr:hal-01062078
SNaP: a Novel Hybrid Method for Circuit Reliability Assessment Under Multiple Faults
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European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF)conference proceeding 2013-10
oai:hal.archives-ouvertes.fr:hal-01062101
Evaluating CLB Designs under Multiple SETs in SRAM-based FPGAs
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IEEE Symp. Defect and Fault Tolerance (DFT) IEEE Symp. Defect and Fault Tolerance (DFT)conference proceeding 2013-10
oai:hal.archives-ouvertes.fr:hal-01062108
SNaP: a Novel Hybrid Method for Circuit Reliability Assessment Under Multiple Faults
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Microelectronics Reliability ISSN:0026-2714article in peer-reviewed journal 2013-07
oai:hal.archives-ouvertes.fr:hal-01062112
Comparison of Fault-Tolerant Fabless CLBs in SRAM-based FPGAs
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IEEE Latin-American Test Workshop (LATW) IEEE Latin-American Test Workshop (LATW)conference proceeding 2013-04
oai:hal.archives-ouvertes.fr:hal-01062116
A New Fault-Tolerant Architecture for CLBs in SRAM-based FPGAs
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IEEE International Conference on Electronics, Circuits, and Systems (ICECS) IEEE International Conference on Electronics, Circuits, and Systems (ICECS)conference proceeding 2012-12
oai:hal.archives-ouvertes.fr:hal-01062119
Automatic Selective Hardening Against Soft Errors: a Cost-based and Regularity-aware Approach
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IEEE International Conference on Electronics, Circuits, and Systems (ICECS) IEEE International Conference on Electronics, Circuits, and Systems (ICECS)conference proceeding 2012-12
oai:hal.archives-ouvertes.fr:hal-01062799
Analyzing and Alleviating the Impact of Errors on an SRAM-based FPGA Cluster
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IEEE International On-Line Testing Symposium (IOLTS) IEEE International On-Line Testing Symposium (IOLTS)conference proceeding 2012-06
oai:hal.archives-ouvertes.fr:hal-01062059
Comparative Study of Defect-Tolerant Multiplexers for FPGAs
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20th IEEE International On-Line Testing Symposium (IOLTS) 20th IEEE International On-Line Testing Symposium (IOLTS)conference proceeding 2014-07
oai:hal.archives-ouvertes.fr:hal-01062064
Cross Logic : A New Approach for Defect-Tolerant Circuits

As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.

IEEE International Conference on IC Design and Technology (ICICDT) IEEE International Conference on IC Design and Technology (ICICDT)conference proceeding 2014-05
oai:hal.archives-ouvertes.fr:hal-01062109
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs
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Microelectronics Reliability ISSN:0026-2714article in peer-reviewed journal 2013-07
oai:hal.archives-ouvertes.fr:hal-01062066
Improving the Robustness of a Switch Box in a Mesh of Clusters FPGA
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15th IEEE Latin American Test Workshop (LATW) 15th IEEE Latin American Test Workshop (LATW)conference proceeding 2014-03
oai:hal.archives-ouvertes.fr:hal-01062075
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs
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European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF)conference proceeding 2013-10
Soutenance
Thèse: "Durcissement de circuits logiques reconfigurables"
Soutenance: 2014-11-14